Hardware/Software Partitioning of Real-Time Systems

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Jakob Axelsson is with the Department of Computer and Information Science, Linköpings University, Sweden


Many high-performance embedded real-time systems are today implemented heterogeneously, with
some parts of the functionality in hardware and others in software. In this paper, we discuss how
hardware/software codesign techniques can be used to improve the design of such systems, and we
focus on hardware/software partitioning and its relation to other important design activities, such as
system behavioural description and hardware architecture selection.


The field of hardware/software codesign has received increasing attention during the last few years,
and numerous publications have appeared describing di erent systems and methodologies (a recent
bibliography lists over 250 publications related to codesign). Most approaches are based on the fact
that a single executable description of a system can nowadays be compiled into either silicon or machine
code, and this opens up the possibility to uniformly describe the behaviour of a system, which will be
implemented in a combination of application-speci fic hardware and software. This description is then
partitioned, with assistance from more or less automatic tools, into separate hardware and software
parts, which are passed on to a high-level synthesis tool respectively a compiler to produce the final

One class of applications particularly well suited for hardware/software codesign is embedded realtime
systems. These systems have well-de ned timing constraints, which are sometimes so severe
that they can only be met in a hardware implementation, but at the same time they might have less
time-critical parts that can bene t from the lower cost and higher
exibility of a software solution.

Therefore, heterogeneous implementations are often necessary for these applications, and are indeed
frequently employed today. But there is a lack of design methodologies and tools that can support
their implementation across the hardware/software technology barrier.